Accompanied with continual development of electronic technologies, various electronic products are becoming more and more compact and versatile with overwhelmingly diversified functions. Therefore, a large number of electronic devices of all types need to be provided in a chip having a relatively small area in order to meet actual requirements of the electronic products.
However, in certain circuit layouts, it happens that the number of electronic devices within a given area becomes too large. That is, a density of the electronic devices in the area is too high, such that routing between the electronic devices within the area becomes infeasible. The circuit layout may not only fail to pass a design rule check, but the circuit itself may also be unable to function normally.
Refer to FIG. 1 showing a circuit layout formed after automatic placement and routing (APR). As shown in FIG. 1, a congestive region 10 is swarmed with quite a number of combinational cells (e.g. NAND and OR logic gates) c to form a serious congestion with a high density of electrical devices. Thus, routing between the electrical devices within the congestive region 10 is extremely challenging such that the circuit layout 1 may not even pass the design rule check.
FIGS. 2A and 2B show schematic diagrams of routing congestions of a circuit layout in a vertical direction. As shown in FIG. 2A, crosses x marked on the circuit layout indicate points that fail to pass the design rule check. It is apparent that these points show arrangements along a vertical direction, and so congestion pointers V1 and V2 represented by arrows in FIG. 2B are indications of the congestions of the circuit layout in the vertical direction.
Similarly, FIGS. 2C and 2D show schematic diagrams of routing congestion of a circuit layout in a horizontal direction. As shown in FIG. 2C, crosses x marked on the circuit layout indicate points that fail to pass the design rule check. It is apparent that these points show arrangements along a horizontal direction, and so congestion pointers H1 and H2 represented by arrows in FIG. 2D are indications of the congestions of the circuit layout in the horizontal direction.
FIGS. 3A and 3B show schematic diagrams illustrating similar routing congestions with similar circuit layouts. Arrangements of hard macros 31 to 34 relative to a circuit layout 30 in FIG. 3A are similar to those of hard macros 31′ to 34′ relative to a circuit layout 30′ in FIG. 3B, so that congestions also appear similar. For example, the hard macros 31′ to 34′ are memories or other electronic devices.
As stated, types and numbers of electronic devices included in a circuit layout are bound to be unceasingly expanding along with continual development of electronic technologies, leading to even more severe congestions of the circuit layout. Hence, there is a need for a congestion preventing apparatus and associated method for solving the above shortcomings.